Method of composite gate formation

ABSTRACT

Methods for forming a nitride barrier film layer in semiconductor devices such as gate structures, and barrier layers, semiconductor devices and gate electrodes are provided. The nitride layer is particularly useful as a barrier to boron diffusion into an oxide film. The nitride barrier layer is formed by selectively depositing silicon onto an oxide substrate as a thin layer, and then thermally annealing the silicon layer in a nitrogen-containing species or exposing the silicon to a plasma source of nitrogen to nitridize the silicon layer.

CROSS REFERENCE TO RELATED APPLICATION

This application is a division of U.S. patent application Ser. No.10/236,841, filed Sep. 6, 2002, currently pending, which is a divisionof U.S. patent application Ser. No. 09/935,255, filed Aug. 22, 2001,currently pending.

FIELD OF THE INVENTION

The present invention relates generally to semiconductor fabricationand, more particularly, to methods of forming nitride barrier layersused in semiconductor devices.

BACKGROUND OF THE INVENTION

Metal-insulator-silicon (MIS) transistors, including metal-oxide-silicon(MOS) transistors, are comprised of doped source and drain regionsformed in the surface of a semiconductor substrate, a channel regionbetween the source and drain, and a gate electrode situated over thechannel region. The gate electrode is physically and electricallyseparated from the channel by a thin gate dielectric (oxide) layer,typically silicon dioxide. The gate electrode typically comprises adoped polysilicon material. Diffusion of dopants such as boron from thedoped polysilicon gate through the gate oxide layer into the underlyingsilicon substrate poses serious problems in processing and thefunctioning of the device.

To inhibit boron diffusion, nitrogen has been incorporated into the gateoxide layer. One conventional method of incorporating nitrogen into theoxide layer is by anneal of the oxide layer in nitric oxide (NO),nitrous oxide (N₂O), ammonia (NH₃) or other nitrogen-containing species.However, thermal nitridation of the gate oxide layer results in nitrogenincorporation at the silicon/oxide interface, which increases theability of the gate oxide layer to suppress boron penetration but canresult in transconductance loss.

Another method of forming a nitrided gate oxide layer is by remoteplasma nitridation by exposing the surface of the oxide layer to aplasma generated species of nitrogen. This results in thepolysilicon/oxide interface being nitridized as opposed to the gateoxide/silicon interface, thus avoiding transconductance loss. However,data indicates that the plasma nitridation may not be scaleable below 25angstroms for integrated circuit (IC) devices with high processingthermal budgets such as DRAMS or flash devices due to the loss ofintegrity of the gate oxide as well as the loss of transconductance dueto the proximity of nitrogen to the gate oxide-silicon interface.

Another conventional method to incorporate nitrogen into the gate oxidelayer is to form a composite gate dielectric layer comprising a siliconnitride layer and an oxide layer. An issue with forming such a compositegate oxide is that the interface between the silicon nitride and oxidelayers typically requires rigorous post-treatment processing toeliminate potential sources of charge trapping. In addition, compositegate dielectrics that comprise nitride and thermal oxides havelimitations due to the total effective oxide thickness that can beachieved due to poor nucleation of nitride on oxide. This requires theformation of a relatively thick nitride layer resulting in an overalleffective oxide thickness that is higher than that which is consideredas usable.

Thus, a need exists for a nitride barrier layer that avoids suchproblems.

SUMMARY OF THE INVENTION

The present invention provides methods for forming a nitride barrierfilm layer useful in fabrication of semiconductor devices such as gatestructures. The nitride layer is particularly useful as a barrier toboron diffusion into an oxide film.

In one aspect, the invention provides methods for forming a nitridebarrier layer over a dielectric (oxide) substrate. The dielectric layeris exposed to a silicon-containing species under low partial pressure,high vacuum to nucleate the surface of the dielectric layer and deposita thin layer of silicon, which is then exposed to a nitrogen-containingspecies to nitridize the silicon and form a silicon nitride barrierlayer. The silicon-containing species can be deposited, for example, byplasma enhanced chemical vapor deposition, low pressure chemical vapordeposition, rapid thermal chemical vapor deposition, among otherprocesses. The silicon layer can comprise polysilicon or amorphoussilicon. In an embodiment of the method, an oxide layer is irradiatedwith a silicon-containing species at a low partial pressure of about10⁻² Torr (10 mTorr) or less to selectively deposit a thin layer ofsilicon onto the oxide surface, preferably about 10 to about 20angstroms thick. The silicon layer can then be thermally annealed in anitrogen-containing species at a preferred temperature of about 700° C.to about 900° C., or exposed to a plasma source of nitrogen to nitridizethe silicon. The plasma nitrogen can be produced, for example, by adownstream microwave system, an electron cyclotron residence system, aninductive coupled plasma system, a radio frequency (RF) system, amongothers.

In another aspect, the invention provides methods for forming asemiconductor device. In one embodiment, the method comprises exposing adielectric layer disposed on a silicon substrate to a silicon-containingspecies under a low partial pressure of about 10⁻² Torr or less, and aflow rate of less than 100 sccm to deposit a layer of about 10 to about20 angstroms silicon; and exposing the silicon layer to anitrogen-containing species to nitridize the silicon and form a siliconnitride barrier layer. The silicon layer can be thermally annealed in anitrogen-containing species, preferably at a temperature of about 700°C. to about 900° C., or exposed to a plasma source of anitrogen-containing species.

In another aspect, the invention provides methods for forming a gateelectrode. In one embodiment, the method comprises exposing a gate oxide(dielectric) layer disposed on a silicon substrate to asilicon-containing species at a low partial pressure of about 10⁻² Torror less to deposit a layer of about 10 to about 20 angstroms silicon;and exposing the silicon layer to a nitrogen-containing species to forma silicon nitride barrier layer. In one embodiment, the silicon layercan be thermally annealed in a nitrogen-containing species, preferablyat a temperature of about 700° C. to about 900° C. In anotherembodiment, the silicon layer can be exposed to a plasma source ofnitrogen. The method can further comprise forming a conductivepolysilicon layer comprising a boron dopant over the nitride barrierlayer, and additional layers as desired including, for example, a metalsilicide layer such as tungsten silicide (WSi_(x)), a barrier layer suchas titanium nitride (TiN), a conductive metal layer such as tungsten(W), and an insulative nitride cap. The nitride barrier layer inhibitspassage of boron from the conductive polysilicon layer into the gateoxide layer.

In another aspect, the invention provides a nitride barrier layer. Thebarrier layer comprises a nitridized silicon layer of about 10 to about20 angstroms formed on an oxide layer by irradiating the oxide layerwith a silicon-containing species under a low partial pressure of about10⁻² Torr or less, and nitridizing the silicon layer to silicon nitrideby exposure to a nitrogen-containing species. In one embodiment, thenitride barrier layer comprises thermally annealed nitridized siliconhaving a thickness of about 10 to about 20 angstroms, and disposedadjacent an oxide layer. In another embodiment, the nitride barrierlayer comprises a plasma nitrogen annealed silicon layer.

In yet another aspect, the invention provides a semiconductor device.The device comprises a semiconductor substrate comprising silicon, anoxide layer disposed adjacent to the semiconductor substrate, and adiffusion barrier layer of about 10 to about 20 angstroms disposedadjacent the oxide layer and comprising a nitridized silicon layerformed by irradiating an oxide layer with a silicon-containing speciesunder low partial pressure of about 10⁻² Torr or less, and nitridizingthe silicon to silicon nitride by exposure to a nitrogen-containingspecies. In one embodiment, the semiconductor device comprises adiffusion barrier layer comprising a thin layer of nitrogen annealedsilicon, the silicon being thermally annealed or plasma annealed in anitrogen-containing species.

In a further aspect, the invention provides a gate electrode. The gateelectrode comprises a gate oxide layer disposed adjacent to asemiconductor substrate, typically silicon, and a diffusion barrierlayer disposed adjacent the gate oxide layer; the diffusion barrierlayer having a thickness of about 10 to about 20 angstroms andcomprising a nitridized silicon layer formed by irradiating the gateoxide layer with a silicon-containing species under low partial pressure(about 10⁻² Torr or less), and nitridizing the silicon to siliconnitride by exposure to a nitrogen-containing species. In one embodiment,the diffusion barrier layer of the gate electrode comprises siliconthermally annealed in a nitrogen-containing species. In anotherembodiment, the gate electrode comprises a diffusion barrier comprisinga plasma nitrogen annealed silicon.

The invention advantageously provides an improved interface between asilicon nitride barrier layer and an underlying dielectric (oxide)layer, having less traps and requiring less post treatment (e.g.,oxidation) of the gate dielectric. In addition, the invention achieves arelatively thin nitride layer thus decreasing the effective oxidethickness as compared to conventionally used methods.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred embodiments of the invention are described below withreference to the following accompanying drawings, which are forillustrative purposes only. Throughout the following views, thereference numerals will be used in the drawings, and the same referencenumerals will be used throughout the several views and in thedescription to indicate same or like parts.

FIG. 1 is a diagrammatic cross-sectional view of a semiconductor waferfragment at a preliminary step of a processing sequence.

FIGS. 2-4 are views of the wafer fragment of FIG. 1 at subsequent andsequential processing steps, showing fabrication of a nitride barrierlayer in a stacked gate electrode according to an embodiment of themethod of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The invention will be described generally with reference to the drawingsfor the purpose of illustrating the present preferred embodiments onlyand not for purposes of limiting the same. The figures illustrateprocessing steps for use in the fabrication of semiconductor devices inaccordance with the present invention. It should be readily apparentthat the processing steps are only a portion of the entire fabricationprocess.

In the current application, the terms “semiconductive wafer fragment” or“wafer fragment” or “wafer” will be understood to mean any constructioncomprising semiconductor material, including but not limited to bulksemiconductive materials such as a semiconductor wafer (either alone orin assemblies comprising other materials thereon), and semiconductivematerial layers (either alone or in assemblies comprising othermaterials). The term “substrate” refers to any supporting structureincluding, but not limited to, the semiconductive wafer fragments orwafers described above.

An embodiment of a method of the present invention is described withreference to FIGS. 1-4, in a method of forming a gate electrode in astacked configuration. The gate electrode generally comprises a stack ofmaterials including a gate oxide (dielectric), a conductively dopedpolysilicon, and can further include a metal silicide layer, a barrierlayer, a conductive layer, and an insulative cap.

While the concepts of the invention are conducive to the fabrication ofgate electrodes, the concepts described herein can be applied to othersemiconductor devices that would likewise benefit from the fabricationof a nitride barrier film as described herein. Therefore, the depictionof the invention in reference to the manufacture of a stacked gateconfiguration is not meant to limit the extent to which one skilled inthe art might apply the concepts taught herein.

Referring to FIG. 1, a portion of a semiconductor wafer 10 is shown at apreliminary processing step. The wafer fragment 10 in progress cancomprise a semiconductor wafer substrate or the wafer along with variousprocess layers formed thereon, including one or more semiconductorlayers or other formations, and active or operable portions ofsemiconductor devices.

The wafer fragment 10 is shown as comprising a semiconductor substrate12, an exemplary substrate being a bulk substrate material ofsemiconductive or semiconductor material, for example, monocrystallinesilicon. The substrate 12 is provided with isolation regions 14 formedtherein, for example, shallow trench isolation regions. A gate oxide(dielectric) layer 16 overlies the substrate 12. The gate oxide layer 16can comprise, for example, silicon dioxide (SiO₂), tantalum pentoxide(Ta₂O₅), hafnium dioxide (HfO₂), and aluminum trioxide (Al₂O₃), amongothers. The gate oxide layer 16 can be formed by conventional methods,and is typically an oxide layer grown directly on the base siliconsubstrate material 12, but can also be a deposited layer.

According to the invention, the gate oxide layer 14 is irradiated with asilicon-containing species under low partial pressure, high vacuumconditions to deposit (nucleate) a thin layer 18 of silicon onto thesurface 16 of the gate oxide layer 14, as shown in FIG. 2. The siliconlayer can comprise polysilicon or amorphous silicon. The processingconditions results in a silicon layer 18 that is thinner than can beachieved under standard silicon growth conditions, i.e., a temperaturegreater than 600° C., and a pressure greater than 100 mTorr, with SiH₂,Si₂H₇, or dichlorosilane (DCS, SiH₂Cl₂). Preferably, the silicon layer18 is less than about 30 angstroms, preferably about 10 to about 20angstroms thick. Exemplary silicon source materials include SiH₂Cl₂,silicon tetrachloride (SiCl₄), and a silicon that contains a hydridesuch as silane (SiH₄), and disilane (Si₂H₆). The silicon material can bedeposited as a layer utilizing any known deposition process includingplasma enhanced chemical vapor deposition (PECVD), low pressure chemicalvapor deposition (LPCVD), and rapid thermal chemical vapor deposition(RTCVD).

Preferably, the silicon material is deposited using a thermal depositionprocess. Processing conditions include a low partial pressure of about10⁻² Torr or less, preferably about 10⁻² to about 10⁻⁷ Torr, preferablyabout 10⁻³ to about 10⁻⁵ Torr, a temperature of about 500° C. to about700° C., with a flow rate of the silicon-containing species of less than100 sccm, preferably about 1 sccm to about 50 sccm, for a duration ofabout 1 second to about 5 minutes.

Referring to FIG. 3, the silicon layer 18 is then nitridized to convertthe silicon to silicon nitride (SiN_(x)) 20 by exposure to anitrogen-containing gas using conventional methods. Such conventionalmethods include a rapid thermal nitridization (RTN), and plasmanitridization, among others. Examples of nitrogen-containing gases foruse in such methods include nitrogen (N₂), ammonia (NH₃), nitrogentrifluoride (NF₃), nitrogen oxides (NO_(x)), and an N₂/He mixture inplasma. The use of a plasma source of nitrogen-containing gas ispreferred.

The nitridation of the silicon layer 18 takes place under conditionsthat are optimal for nitridation of silicon. An example and preferredrapid thermal nitridization includes exposing the silicon layer toammonia (NH₃) or other nitrogen-containing ambient at a temperature ofabout 700° C. to about 900° C., a pressure of about 1 to about 760 Torr,with a flow rate of about 100 sccm to about 10,000 sccm, for a durationof about 1 second to about 180 minutes. The partial pressure of thenitrogen-containing ambient can range from a low partial pressure, forexample, of about 1 to about 10 Torr, up to full atmospheric pressure tooptimize processing as desired.

In a plasma nitridization of the silicon layer 18, the plasma stream canbe produced by a variety of plasma sources, such as a downstreammicrowave system, an electron cyclotron residence (ECR) system, aninductive coupled plasma (ICP) system, a radio frequency (RF) system,among others. Exemplary plasma nitridization processes comprise exposingthe wafer 10 to a remote microwave plasma source of nitrogen or aninductive coupled plasma (ICP) at a pressure of about 1 to about 20Torr. The plasma typically comprises the nitrogen-containing gas,preferably nitrogen (N₂) or ammonia (NH₃), and an inert gas such ashelium or argon to increase the plasma density.

The resulting nitride layer 20 functions as a barrier to inhibit thepassage of boron through the gate dielectric layer from an overlyingboron-doped gate polysilicon layer into the substrate 12.

The structure can then be processed by conventional methods to completethe gate electrode. An example of a gate stack comprises a gate oxidelayer 16, a doped polysilicon layer 22, a barrier layer 24 such astungsten nitride (WN), a layer 26 of tungsten or other conductive metal,and a nitride cap 28, as shown in FIG. 4. Another example of a gatestack (not shown) comprises a gate oxide, a doped polysilicon, tungstensilicide (WSi_(x)), titanium silicide (TiSi_(x)), cobalt silicide(CoSi_(x)), and a nitride cap. The gate layers can then be patterned andetched utilizing photolithographic processing (i.e., by dry etching) toform a transistor gate stack 30, as shown. Sidewalls 32 are providedadjacent the transistor gate, and can comprise, for example, silicondioxide or silicon nitride.

Thereafter, a dopant implantation, typically with an n-typeconductivity-enhancing dopant, can be performed to form the source/drain(S/D) regions 34 in the silicon substrate 12 proximate the gate 30. Thesource/drain regions together with the gate form an operative fieldeffect transistor device.

In compliance with the statute, the invention has been described inlanguage more or less specific as to structural and methodical features.It is to be understood, however, that the invention is not limited tothe specific features shown and described, since the means hereindisclosed comprise preferred forms of putting the invention into effect.The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. A gate electrode, comprising: a gate dielectric layer overlying asubstrate; and a diffusion barrier layer on the gate dielectric layer,the barrier layer having a thickness of up to about 30 angstroms andcomprising chemical vapor deposited and nitridized silicon, thediffusion barrier layer effective to inhibit diffusion of a dopantmaterial therethrough.
 2. A gate electrode, comprising: a gatedielectric layer overlying a substrate; and a diffusion barrier layer onthe gate dielectric layer and comprising chemical vapor deposited andnitridized silicon, the diffusion barrier layer having a thickness of upto about 20 angstroms, and effective to inhibit diffusion of a dopantmaterial therethrough into the gate dielectric layer.
 3. A gateelectrode, comprising: a gate dielectric layer on a substrate; and adiffusion barrier layer on the gate dielectric layer and comprisingchemical vapor deposited and nitridized silicon, the diffusion barrierlayer having a thickness of up to about 20 angstroms, and effective toinhibit diffusion of a boron therethrough into the gate dielectriclayer.
 4. A gate electrode, comprising: a gate dielectric layer on asubstrate; a diffusion barrier layer of up to about 30 angstroms on thegate dielectric layer; the diffusion barrier layer comprising chemicalvapor deposited and nitridized silicon; and a polysilicon layercomprising a conductivity enhancing dopant on the diffusion barrierlayer; wherein the diffusion barrier layer is effective to inhibitdiffusion of dopant therethrough into the gate dielectric layer.
 5. Agate electrode, comprising: a gate dielectric layer on a substrate; adiffusion barrier layer of up to about 30 angstroms over the gatedielectric layer; the diffusion barrier layer comprising chemical vapordeposited and nitridized silicon; a polysilicon layer comprising aconductivity enhancing dopant over the diffusion barrier layer; and abarrier layer overlying the polysilicon layer; wherein the diffusionbarrier layer is effective to inhibit diffusion of dopant therethroughinto the gate dielectric layer.
 6. A gate electrode, comprising: a gatedielectric layer on a substrate; a diffusion barrier layer of up toabout 30 angstroms over the gate dielectric layer; the diffusion barrierlayer comprising chemical vapor deposited and nitridized silicon; apolysilicon layer comprising a conductivity enhancing dopant on thediffusion barrier layer; a barrier layer overlying the polysiliconlayer; and a conductive metal layer over the barrier layer; wherein thediffusion barrier layer is effective to inhibit diffusion of dopanttherethrough into the gate dielectric layer.
 7. A gate electrode,comprising: a gate dielectric layer on a substrate; a diffusion barrierlayer of up to about 30 angstroms over the gate dielectric layer; thediffusion barrier layer comprising chemical vapor deposited andnitridized silicon; a polysilicon layer comprising a conductivityenhancing dopant on the diffusion barrier layer; a barrier layeroverlying the polysilicon layer; a conductive metal layer over thebarrier layer; and an insulative layer overlying the conductive metallayer; wherein the diffusion barrier layer is effective to inhibitdiffusion of dopant therethrough into the gate dielectric layer.
 8. Agate electrode, comprising: a gate dielectric layer on a substrate; adiffusion barrier layer of up to about 30 angstroms over the gatedielectric layer; the diffusion barrier layer comprising chemical vapordeposited and nitridized silicon; a polysilicon layer comprising aconductivity enhancing dopant on the diffusion barrier layer; and ametal silicide layer over the polysilicon layer; wherein the diffusionbarrier layer is effective to inhibit diffusion of dopant therethroughinto the gate dielectric layer.
 9. A gate electrode, comprising: a gatedielectric layer on a substrate; a diffusion barrier layer of up toabout 30 angstroms over the gate dielectric layer; the diffusion barrierlayer comprising chemical vapor deposited and nitridized silicon; apolysilicon layer comprising a conductivity enhancing dopant over thediffusion barrier layer; a metal silicide layer over the polysiliconlayer; and an insulative layer over the metal silicide layer; whereinthe diffusion barrier layer is effective to inhibit diffusion of dopanttherethrough into the gate dielectric layer.
 10. A gate electrode,comprising: a gate oxide layer overlying a substrate; and a diffusionbarrier layer over the gate oxide layer; the diffusion barrier layerhaving a thickness of about 10-20 angstroms and comprising a nitridizedsilicon layer deposited by irradiating an oxide layer with a silicon gasunder low partial pressure, and nitridizing the silicon layer byexposure to a nitrogen gas.
 11. A gate electrode, comprising: a gateoxide layer overlying a substrate; and a diffusion barrier layeroverlying the oxide layer, and comprising a nitridized silicon layerhaving a thickness of about 10-20 angstroms.
 12. A gate electrode,comprising: a gate oxide layer overlying a substrate; and a diffusionbarrier layer overlying the gate oxide layer, and comprising nitrogenannealed silicon and having a thickness of about 10-20 angstroms. 13.The electrode of claim 12, wherein the diffusion barrier layer comprisesplasma annealed silicon.
 14. The electrode of claim 12, wherein thediffusion barrier layer comprises thermally annealed silicon.
 15. A gateelectrode, comprising: a gate dielectric layer overlying a substrate;and a diffusion barrier layer of about 30 angstroms or less over thegate dielectric layer, and comprising nitridized and chemical vapordeposited silicon.
 16. The gate electrode of claim 15, wherein thediffusion barrier layer is about 10-20 angstroms.
 17. A gate electrode,comprising: a gate dielectric layer overlying a substrate; a diffusionbarrier layer of about 30 angstroms or less over the gate dielectriclayer, and comprising nitridized and chemical vapor deposited silicon; aconductive layer over the diffusion barrier layer; and an insulativelayer over the conductive layer.
 18. A gate electrode, comprising: agate dielectric layer overlying a substrate; a diffusion barrier layerof about 30 angstroms or less over the gate dielectric layer, andcomprising nitridized and chemical vapor deposited silicon; a dopedpolysilicon layer over the diffusion barrier layer; and an insulativelayer over the doped polysilicon layer; wherein the diffusion barrierlayer inhibits passage of dopant from the polysilicon layer to thesubstrate.
 19. A gate electrode, comprising: a gate dielectric layeroverlying a substrate; a diffusion barrier layer of about 30 angstromsor less over the gate dielectric layer, and comprising nitridized andchemical vapor deposited silicon; a doped polysilicon layer over thediffusion barrier layer; a barrier layer over the doped polysiliconlayer; a conductive metal layer over the barrier layer; and aninsulative layer over the doped polysilicon layer; wherein the diffusionbarrier layer inhibits passage of dopant from the polysilicon layer tothe substrate.
 20. A gate electrode, comprising: a gate dielectric layeroverlying a substrate; a diffusion barrier layer of about 30 angstromsor less over the gate dielectric layer, and comprising nitridized andchemical vapor deposited silicon; a doped polysilicon layer over thediffusion barrier layer; a metal silicide layer over the dopedpolysilicon layer; and an insulative nitride layer disposed over themetal silicide layer; wherein the diffusion barrier layer inhibitspassage of dopant from the polysilicon layer to the substrate.
 21. Agate electrode, comprising: a gate dielectric layer on a substrate; anda diffusion barrier layer of about 30 angstroms or less over the gatedielectric layer; the diffusion barrier layer comprising plasma nitrogenannealed silicon.
 22. A gate electrode, comprising: a gate dielectriclayer on a substrate; and a diffusion barrier layer of about 30angstroms or less over the gate dielectric layer; the diffusion barrierlayer comprising thermally annealed nitridized silicon.
 23. A gateelectrode, comprising: a gate dielectric layer on a substrate; and adiffusion barrier layer of about 30 angstroms or less over the gatedielectric layer; the diffusion barrier layer comprising nitridized andchemical vapor deposited silicon.
 24. A gate electrode, comprising: agate dielectric layer on a substrate; and a diffusion barrier layer ofabout 10-20 angstroms over the gate dielectric layer; the diffusionbarrier layer comprising nitridized and chemical vapor depositedsilicon; a conductive layer over the diffusion barrier layer; and aninsulative layer over the conductive layer.
 25. A gate electrode,comprising: a gate dielectric layer on a substrate; a diffusion barrierlayer of about 10-20 angstroms over the gate dielectric layer; thediffusion barrier layer comprising nitridized and chemical vapordeposited silicon; a doped polysilicon layer over the diffusion barrierlayer; and an insulative layer disposed on the doped polysilicon layer;wherein the diffusion barrier layer inhibits passage of dopant from thepolysilicon layer through the barrier layer.
 26. A gate electrode,comprising: a gate dielectric layer on a substrate; and a diffusionbarrier layer of about 10-20 angstroms over the gate dielectric layer;the diffusion barrier layer comprising nitridized and chemical vapordeposited silicon; a doped polysilicon layer over the diffusion barrierlayer; a barrier layer over the doped polysilicon layer; a conductivemetal layer over the barrier layer; and an insulative layer over theconductive metal layer; wherein the diffusion barrier layer inhibitspassage of dopant from the polysilicon layer through the barrier layer.27. A gate electrode, comprising: a gate dielectric layer on asubstrate; and a diffusion barrier layer of about 10-20 angstroms overthe gate dielectric layer; the diffusion barrier layer comprisingnitridized and chemical vapor deposited silicon; a doped polysiliconlayer over the diffusion barrier layer; a metal silicide layer over thedoped polysilicon layer; and an insulative nitride layer over the metalsilicide layer; wherein the diffusion barrier layer inhibits passage ofdopant from the polysilicon layer through the barrier layer.
 28. A gateelectrode, comprising: a gate oxide layer overlying a semiconductorsubstrate; and a diffusion barrier layer over the gate oxide layer; thediffusion barrier layer comprising a nitridized silicon layer formed byexposure of an oxide layer to a silicon gas under low partial pressureto form a silicon layer of about 10-20 angstroms, and exposure of thesilicon layer to a nitrogen gas to nitridize a surface of the siliconlayer, the diffusion barrier layer effective to inhibit passage of adopant material therethrough.
 29. A gate electrode, comprising: a gateoxide layer overlying a semiconductor substrate; and a diffusion barrierlayer over the gate oxide layer; the diffusion barrier layer comprisinga nitridized silicon layer formed by exposure of an oxide layer to asilicon gas under low partial pressure and high vacuum to form a siliconlayer having a thickness of up to about 30 angstroms, and exposure ofthe silicon layer to a nitrogen gas to nitridize the silicon layer andform a silicon nitride barrier layer, the barrier layer effective toinhibit diffusion of a dopant material therethrough.
 30. An integratedcircuit transistor gate stack, comprising: a gate dielectric layer; anda nitride barrier layer in contact with the dielectric layer, thebarrier layer comprising nitridized and chemical vapor deposited siliconand having a thickness of about 30 angstroms or less.
 31. An integratedcircuit transistor gate stack, comprising: a gate dielectric layer; anda nitride barrier layer in contact with the dielectric layer, thebarrier layer comprising thermally annealed nitridized silicon andhaving a thickness of about 30 angstroms or less.
 32. An integratedcircuit transistor gate stack, comprising: a gate dielectric layer; anda nitride barrier layer in contact with the dielectric layer, thebarrier layer comprising plasma nitrogen annealed silicon and having athickness of about 30 angstroms or less.
 33. An integrated circuit,comprising: a transistor comprising a gate stack situated adjacentsource/drain regions in a substrate, the gate stack comprising a gatedielectric layer overlying the substrate, and a nitride barrier layerover the gate dielectric layer, the nitride barrier layer comprisingnitridized and chemical vapor deposited silicon and having a thicknessof about 30 angstroms or less.
 34. The circuit of claim 33, being DRAM.35. The circuit of claim 33, being a flash device.
 36. An integratedcircuit, comprising: a transistor comprising a gate stack situatedadjacent source/drain regions in a substrate, the gate stack comprisinga gate dielectric layer overlying the substrate, and a nitride barrierlayer over the gate dielectric layer, the nitride barrier layercomprising thermally annealed nitridized silicon and having a thicknessof about 30 angstroms or less.
 37. An integrated circuit, comprising: atransistor comprising a gate stack situated adjacent source/drainregions in a substrate, the gate stack comprising a gate dielectriclayer overlying the substrate, and a nitride barrier layer over the gatedielectric layer, the nitride barrier layer comprising plasma nitrogenannealed silicon and having a thickness of about 30 angstroms or less.38. A substrate supporting a gate structure, the gate structurecomprising: a layer of gate dielectric overlying the substrate; and anitride barrier layer over the gate dielectric layer, the barrier layercomprising nitridized and chemical vapor deposited silicon and having athickness of about 30 angstroms or less.
 39. A substrate supporting agate structure, the gate structure comprising: a layer of gatedielectric overlying the substrate; and a nitride barrier layer over thegate dielectric layer, the barrier layer comprising thermally annealednitridized silicon and having a thickness of about 30 angstroms or less.40. A substrate supporting a gate structure, the gate structurecomprising: a layer of gate dielectric overlying the substrate; and anitride barrier layer over the gate dielectric layer, the barrier layercomprising plasma nitrogen annealed silicon and having a thickness ofabout 30 angstroms or less.